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Data Sheet No. PD94252
IRU3047
DUAL SYNCHRONOUS PWM CONTROLLER WITH CURRENT SHARING CIRCUITRY AND LDO CONTROLLER
PRELIMINARY DATA SHEET
FEATURES
Dual Synchronous Controller in 20-Pin Package with 1808 out-of-phase operation LDO Controller with 40mA drive Can be configured as 2-Independent or 2-Phase PWM Controller Programmable Current Sharing in 2-Phase Configuration Flexible, Same or Separate Supply Operation Operation from 4V to 25V Input Internal 200KHz Oscillator per phase Soft-Start controls all outputs Fixed Frequency Voltage Mode 500mA Peak Output Drive Capability Short Circuit Protection for All Outputs Power Good Output
DESCRIPTION
The IRU3047 IC combines a Dual synchronous Buck controller and a linear regulator controller, providing a cost-effective, high performance and flexible solution for multi-output applications. The Dual synchronous controller can be configured as 2-independent or 2-phase controller. In 2-phase configuration, the IRU3047 provides a programmable current sharing which is ideal when the output power exceeds any single input power budget. IRU3047 provides a separate adjustable output by driving a switch as a linear regulator. This device features an internal 200KHz oscillator, under-voltage lockout for all input supplies, an external programmable soft-start function as well as output under-voltage detection that latches off the device when an output short is detected.
APPLICATIONS
Dual-Phase Power Supply DDR Memory Source Sink Vtt Application Graphic Card Hard Disk Drive Power supplies requiring multiple outputs
TYPICAL APPLICATION
12V L1 5V C1 C2 C3 C4 VCL Vcc C5 3.3V C6 VOUT2 C7 R2 C8 C9 R3 R4 Comp2 HDrv2 Comp1 Q1 R1 Fb3 VOUT3 LDrv1 Q3 VcH1 VcH2 HDrv1 Q2 C13 C12 L2
D1
D2
C11
C14 L3 R5 VOUT1 C16
U1 IRU3047
PGnd VREF Vp2 Fb1 Fb2 C17 Q4 L4 R9
R7
R8
PGood C10
PGood SS
LDrv2 Gnd
Q5
Figure 1 - Typical application of IRU3047 configured as 2-phase converter.
PACKAGE ORDER INFORMATION
TA (C) 0 To 70
Rev. 1.0 09/09/02
DEVICE IRU3047CW
PACKAGE 20-Pin Plastic SOIC (W)
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IRU3047
ABSOLUTE MAXIMUM RATINGS
Vcc Supply Voltage .................................................. 25V VCH1, VCH2 and VCL Supply Voltage ........................... 30V (not rated for inductive load) Storage Temperature Range ...................................... -65C To 150C Operating Junction Temperature Range ..................... 0C To 125C
PACKAGE INFORMATION
20-PIN PLASTIC SOIC WB (W)
TOP VIEW VREF 1 Vp2 2 Fb2 3 Vcc 4 Comp1 5 Comp2 6 VcH2 7 HDrv2 8 LDrv2 9 PGnd 10 20 Gnd 19 P G o o d 18 Fb1 17 SS 16 Fb3 15 VOUT3 14 VcH1 13 HDrv1 12 LDrv1 11 VCL
uJA=758C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=5V, VcH1=VcH2=VCL=12V and TA=0 to 70C. Typical values refer to TA=25C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER Reference Voltage Section Fb Voltage Fb Voltage Line Regulation UVLO Section UVLO Threshold - Vcc UVLO Hysteresis - Vcc UVLO Threshold - VccLDO UVLO Hysteresis - VccLDO UVLO Threshold - VcH1 UVLO Hysteresis - VcH1 UVLO Threshold - VcH2 UVLO Hysteresis - VcH2 UVLO Threshold - Fb UVLO Hysteresis - Fb Supply Current Section Vcc Dynamic Supply Current VcH1 Dynamic Supply Current VcH2 Dynamic Supply Current Vcc Static Supply Current VcH1 Static Supply Current VcH2 Static Supply Current SYM VFB LREG UVLOVCC TEST CONDITION MIN 1.225 5UVLOVCCLDO Supply Ramping Up UVLOVCH1 Supply Ramping Up UVLOVCH2 Supply Ramping Up UVLOFb Fb Ramping Down
Dyn ICC Dyn ICH1 Dyn ICH2 ICCQ ICH1Q ICH2Q
Freq=200KHz, CL=1500pF Freq=200KHz, CL=1500pF Freq=200KHz, CL=1500pF SS=0V SS=0V SS=0V
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PARAMETER Soft-Start Section Charge Current Power Good Section Fb1 Lower Trip Point Fb1 Upper Trip Point Fb2 Lower Trip Point Fb2 Upper Trip Point Fb3 Lower Trip Point Fb3 Upper Trip Point Power Good Voltage OK Error Amp Section Fb Voltage Input Bias Current Fb Voltage Input Bias Current Transconductance 1 Transconductance 2 Input Offset Voltage for PWM2 Oscillator Section Frequency Ramp Amplitude Output Drivers Section Rise Time Fall Time Dead Band Time Max Duty Cycle Min Duty Cycle LDO Controller Section Drive Current Fb Voltage Input Bias Current SYM SSIB PGFB1L PGFB1H PGFB2L PGFB2H PGFB3L PGFB3H VPG IFB1 IFB2 gm1 gm2 VOS(ERR)2 Freq VRAMP Tr Tf TDB TON TOFF ILDO VFBLDO ILDO(BIAS) TEST CONDITION SS=0V Fb1 Ramping Down Fb1 Ramping Up Fb2 Ramping Down Fb2 Ramping Up Fb3 Ramping Down Fb3 Ramping Up 5K resistor pulled up to 5V SS=3V SS=0V MIN 15 TYP 25 0.9VREF 1.1VREF 0.9VREF 1.1VREF 0.9VREF 1.1VREF 4.8 -0.1 -64 400 600 0 200 1.25 35 50 150 90 0 45 1.25 0.5 MAX 30 UNITS mA V V V V V V V mA mA mmho mmho mV KHz V ns ns ns % % mA V mA
4.5
5
Fb2 to VP2 Rt=Open
-2 180
+2 220
CL=1500pF CL=1500pF Fb=1V, Freq=200KHz Fb=1.5V 50 85 0 30 1.225
100 100 250
1.275 2
PIN DESCRIPTIONS
PIN# 1 2 PIN SYMBOL VREF Vp2 PIN DESCRIPTION Reference Voltage. Non-inverting input to the second error amplifier, in the current sharing mode it is connected to the programming resistor. In independent two channel mode it is connected to the reference voltage (Pin1) when Fb2 is connected to the resistor divider to set the output voltage. Inverting inputs to the error amplifiers, in current sharing mode Fb1 is connected to a resistor divider to set the output voltage and Fb2 is connected to programming resistor to achieve current sharing. In independent two channel mode, these pins work as feedback inputs for each channel. Supply voltage for the internal blocks of the IC. Compensation pins for the error amplifiers. Supply voltage for the high side output drivers. These are connected to voltages that must be at least 4V higher than their bus voltages (assuming 5V threshold MOSFET). A minimum of 1mF high frequency capacitor must be connected from these pins to PGnd pin to provide peak drive current capability. Output driver for high side power MOSFET. Connect a diode, such as BAT54 or 1N4148, from these pins to ground for the application when the inductor current goes negative (Source/Sink), soft-start at no load and for fast load transient from full load to no load. www.irf.com
3,18
Fb2, Fb1
4 Vcc 5,6 Comp1, Comp2 7,14 VcH2, VcH1
8,13
HDrv2, HDrv1
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PIN# 9,12 10 11 15 16 17 19 20 PIN SYMBOL LDrv2, LDrv1 PGnd VCL VOUT3 Fb3 SS PGood Gnd PIN DESCRIPTION Output driver for the synchronous power MOSFET. This pin serves as the separate ground for MOSFET's driver and should be connected to the system's ground plane. Supply voltage for the low side output drivers. Driver signal for the LDO's external transistor. LDO's feedback pin, connected to a resistor divider to set the output voltage of LDO. Soft-Start pin. The converter can be shutdown by pulling this pin below 0.5V. Power Good pin. This pin is a collector output that switches Low when any of the outputs are outside of the specified under voltage trip point. Ground pin.
BLOCK DIAGRAM
Vcc 4
Bias Generator 64uA Max 4.2V / 4.0V 3V 1.25V POR
14 V c H 1
25uA
13 HDrv1
SS 17
UVLO VcH1 VcH2 3.5V / 3.3V 3.5V / 3.3V
11 VCL
POR PWM Comp1 Error Amp1 1.25V 25K
12 LDrv1 R
25K
Fb1 18 S Comp1
Q
Reset Dom
5
Ramp1 Two Phase Oscillator Ramp2
Set1 SS > 2V
7 VcH2
8 HDrv2
Set2
VREF 1
1.25V
S
PWM Comp2 25K Error Amp2
Q R
Reset Dom
Vp2
2
25K
9 LDrv2
Fb2
3
0.5V
10 PGnd
POR
Comp2
6
Fb2 Monitor Shut Down Vcc 25K 1.25V Fb1 Fb2 Fb3 PGood
19 PGood
15 VOUT3 Fb3 16 Gnd 20
25K 2V 40mA LDO Controller SS
Figure 2 - Block diagram of the IRU3047.
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THEORY OF OPERATION
Introduction The IRU3047 is designed for multi-outputs applications. It includes two synchronous buck controllers and a linear regulator controller. The two synchronous controller operates with fixed frequency voltage mode and can be configured as two independent controller or 2-phase controller with current sharing. The timing of the IC is provided through an internal oscillator circuit. These are two out of phase oscillators with 200KHz switching frequency. Independent Mode In this mode the IRU3047 provides two independent outputs with either common or different input voltages. The output voltage of the individual channel is set and controlled by the output of the error amplifier, this is the amplified error signal from the sensed output voltage and the reference voltage. This voltage is compared to the ramp signal and generates fixed frequency pulses of variable duty-cycle, which drives the two N-channel external MOSFETs. Current Sharing Mode In the current sharing mode, the two converter's outputs tied together and provide one single output (see Figure 1). In this mode, one control loop acts as a master and sets the output voltage as a regular Voltage Mode buck controller and the other control loop acts as a slave and monitors the current information for current sharing. The current sharing is programmable and sets by using two external resistors in output currents' path. The slave's error amplifier, error amplifier 2 (see the block diagram) measures the voltage drops across the current sense resistors, the differential of these signals is amplified and compared with the ramp signal and generate the fixed frequency pulses of variable duty cycle to match the output currents. Out of Phase Operation The IRU3047 drives its two output stages 180o out of phase. In 2-phase configuration, the two inductor ripple currents cancel each other and result to a reduction of the output current ripple and contributes to a smaller output capacitors for the same ripple voltage requirement. In application with single input voltage, the 2-phase configuration reduces the input ripple current. This results in much smaller RMS current in the input capacitor and reduction of input capacitor. Soft-Start The IRU3047 has a programmable soft start to control the output voltage rise and limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Vcc, VcH1 and VcH2 rise above their threshold and generates the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the E/ A's output of the PWM converter. As the charging voltage of the external capacitor ramps up, the PWM signals increase from zero to the point the feedback loop takes control. Shutdown The converter can be shutdown by pulling the soft-start pin below 0.5V. This can be easily done by using an external small signal transistor. During shutdown the MOSFET drivers and the LDO controller turn off. Power Good The IRU3047 provides a power good signal. This is an open collector output and it is pulled low if the output voltages are not within the specified threshold. This pin can be left floating if not used. Short-Circuit Protection The outputs are protected against the short circuit. The IRU3047 protects the circuit for shorted output by sensing the output voltages. The IRU3047 shuts down the PWM signals and LDO controller, when the output voltages drops below the set values. Under-Voltage Lockout The under-voltage lockout circuit assures that the MOSFET driver outputs and LDO controller remain in the off state whenever the supply voltages drop below set parameters. Normal operation resumes once the supply voltages rise above the set values.
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APPLICATION INFORMATION
Design Example: The following example is a typical application for IRU3047 in current sharing mode. The schematic is Figure 12 on page 16. VIN1(MASTER) = 12V VIN2(SLAVE) = 5V VOUT1 = 1.5V IOUT = 12A DVOUT = 75mV fS = 200KHz PWM Section Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb1 pin is the inverting input of the error amplifier, which is internally referenced to 1.25V. The divider is ratioed to provide 1.25V at the Fb1 pin when the output is at its desired value. The output voltage is defined by using the following equation: VOUT1 = VREF3 1+ Boost Supply Vc To drive the high-side switch it is necessary to supply a gate voltage at least 4V greater than the bus voltage. This is achieved by using a charge pump configuration as shown in Figure 1. The capacitor is charged up to approximately twice the bus voltage. A capacitor in the range of 0.1mF to 1mF is generally adequate for most applications. Sense Resistor Selection These resistors will determine the current sharing between two channels. The relationship between the Master and Slave output currents is expressed by: RSEN13IMASTER = RSEN23ISLAVE ---(3) Soft-Start Programming The soft-start timing can be programmed by selecting the soft start capacitance value. The start up time of the converter can be calculated by using:
tSTART = 753Css (ms)
---(2)
Where: CSS is the soft-start capacitor (mF) For a start-up time of 75ms, the soft-start capacitor will be 1mF. Choose a ceramic capacitor at 1mF.
(
R6 R5
)
---(1)
When an external resistor divider is connected to the output as shown in Figure 3.
VOUT1 IRU3047
Fb1 R5 R6
For an equal current sharing, RSEN1=RSEN1 Choose RSEN1=RSEN2=5mV Input Capacitor selection The input filter capacitor should be based on how much ripple the supply can tolerate on the DC input line. The ripple current generated during the on time of control MOSFET should be provided by input capacitor. The RMS value of this ripple is expressed by: IRMS = IOUT D3(1-D) ---(4)
Figure 3 - Typical application of the IRU3047 for programming the output voltage. Equation (1) can be rewritten as: R6 = R5 3
( VOUT1 - 1) VREF
Will result to: VOUT1 = 2.5V VREF = 1.25V R5 = 1K R6 = 1K
Where: D is the Duty Cycle, simply D=VOUT/VIN. IRMS is the RMS value of the input capacitor current. IOUT is the output current for each channel. For VIN1=12V, IOUT1=6A and D1=0.208 Results to: IRMS1=2.43A And for VIN2=5V, IOUT2=6A and D2=0.5 Results to: IRMS2 =3A
If the high value feedback resistors are used, the input bias current of the Fb pin could cause a slight increase in output voltage. The output voltage set point can be more accurate by using precision resistor.
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For higher efficiency, a low ESR capacitor is recommended. For VIN1=12V, choose two Poscap from Sanyo 16TPB47M (16V, 47mF, 70mV, 1.4A) For VIN2=5V, choose two 6TPB330M (6.3V, 330mF, 40mV, 3A). Output Capacitor Selection The criteria to select the output capacitor is normally based on the value of the Effective Series Resistance (ESR). In general, the output capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. The ESR of the output capacitor is calculated by the following relationship: ESR [ DVO DIO ---(5) For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: Di 1 VOUT VIN - VOUT = L3 ; Dt = D3 ;D= Dt fS VIN VOUT L = (VIN - VOUT)3 ---(6) VIN3Di3fS Where: VIN = Maximum Input Voltage VOUT = Output Voltage i = Inductor Ripple Current fS = Switching Frequency t = Turn On Time D = Duty Cycle For Di1=30% of I1, we get L3=5.46mH For Di2=30% of I2, we get: L4=3.47mH The Coilcraft DO5022HC series provides a range of inductors in different values and low profile for large currents. For L3 choose DO5022P-602HC (6mH, 7.5A) For L4 choose DO5022P-472HC (4.7mH, 8.4A) Power MOSFET Selection The selections criteria to meet power transfer requirements is based on maximum drain-source voltage (VDSS), gate-source drive voltage (VGS), maximum output current, On-resistance RDS(ON) and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (VIN). The gate drive requirement is almost the same for both MOSFETs. Caution should be taken with devices at very low VGS to prevent undesired turn-on of the complementary MOSFET, which results a shoot-through current. The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter the average inductor current is equal to the DC load current. The conduction loss is defined as: PCOND(Upper Switch) = ILOAD3RDS(ON)3D3q PCOND(Lower Switch) = ILOAD3RDS(ON)3(1 - D)3q q = RDS(ON) Temperature Dependency The total conduction loss is defined as:
PCON(TOTAL)=PCON(Upper Switch)q+PCON(Lower Switch)q
2 2
Where: DVO = Output Voltage Ripple DIO = Output Current DVO=100mV and DIO=5A, results to ESR=20mV The Sanyo TPC series, PosCap capacitor is a good choice. The 6TPB470M 470mF, 6.3V has an ESR 40mV. Selecting two of these capacitors in parallel, results to an ESR of 20mV which achieves our low ESR goal. The capacitor value must be high enough to absorb the inductor's ripple current. The larger the value of capacitor, the lower will be the output ripple voltage. The resulting output ripple current is smaller then each channel ripple current due to the 1808 phase shift. These currents cancel each other. The cancellation is not the maximum because of the different duty cycle for each channel. Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. Low inductor value causes large ripple current, resulting in the smaller size, but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor (i); the optimum point is usually found between 20% and 50% ripple of the output current.
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The RDS(ON) temperature dependency should be considered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. Choose IRF7811A for control MOSFET and IRF7809A for synchronous MOSFET. These devices provide low on-resistance in a compact SOIC 8-Pin package. The MOSFETs have the following data: IRF7811A IRF7809A VDSS = 28V VDSS = 20V ID = 11.2A @ 908C ID = 14.2A @ 908C RDS(ON) = 12mV @ RDS(ON) = 8.5mV @ VGS = 4.5V VGS = 4.5V For both: q = 1.5 for 1508C (Junction Temperature) The total conduction losses for the master channel is: PCON(MASTER) = 0.498W The total conduction losses for the slave channel is: PCON(SLAVE) = 0.5535W The control MOSFET contributes to the majority of the switching losses in synchronous Buck converter. The synchronous MOSFET turns on under zero-voltage condition, therefore the turn on losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: VDS(OFF) tr + tf 3 3 ILOAD ---(7) 2 T Where: VDS(OFF) = Drain to Source Voltage at off time tr = Rise Time tf = Fall Time T = Switching Period ILOAD = Load Current PSW =
VDS 90%
0dB -40dB/decade 08
From IRF7811A data sheet we obtain: IRF7811A tr = 4ns tf = 8ns These values are taken under a certain condition test. For more detail please refer to the IRF7811A and IRF7809A data sheets. By using equation (7), we can calculate the switching losses. PSW(MASTER) = 86.4mW PSW(SLAVE) = 36mW Feedback Compensation The control scheme for master and slave channels is based on voltage mode control, but the compensation of these two feedback loops is slightly different. The Master channel sets the output voltage and its feedback loop should take care of double pole introduced by the output filter as a regular voltage mode control loop. The goal is to provide a close loop transfer function with the highest 0dB crossing frequency and adequate phase margin. The slave feedback loop acts slightly different and its goal is using the current information for current sharing. The master feedback loop sees the output filter. The output LC filter introduces a double pole, -40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 1808 (see Figure 5). The Resonant frequency of the LC filter expressed as follows: FLC(MASTER) = 1 2p Lo3Co ---(8)
Figure 5 shows gain and phase of the LC filter. Since we already have 1808 phase shift just from the output filter, the system risks being unstable.
Gain Phase
10% VGS td(ON) tr td(OFF) tf
-1808 FLC Frequency
FLC
Frequency
Figure 5 - Gain and phase of LC filter.
Figure 4 - Switching time waveforms.
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The master error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or AC phase compensation. The E/A can be compensated with or without the use of local feedback. When operated without local feedback the transconductance properties of the E/A become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp1 pin to ground as shown in Figure 6. The ESR zero of the LC filter expressed as follows: FESR = 1 2p3ESR3Co
VOUT R6 Fb1 Comp1 R5 VREF
Gain(dB)
First select the desired zero-crossover frequency (Fo): FO1 > FESR and FO1 [ (1/5 ~ 1/10)3 fS Use the following equation to calculate R4: R4 = 1 VOSC FO13FESR R5 + R6 3 3 3 gm VIN(MASTER) FLC2 R5 ---(13)
---(9)
E/A1 C9 R4
V e
Where: VIN(MASTER) = Maximum Input Voltage VOSC = Oscillator Ramp Voltage FO1 = Crossover Frequency for the master E/A FESR = Zero Frequency of the Output Capacitor FLC(MASTER) = Resonant Frequency of Output Filter gm = Error Amplifier Transconductance R5 and R6 = Resistor Dividers for Output Voltage Programming For: VIN(MASTER) = 12V VOSC = 1.25V FO1 = 15KHz FESR = 8.4KHz FLC(MASTER) = 2.1KHz R5 = R6 = 1KV gm = 600mmho This results to R4=9.8KV. Choose R4=10KV To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole:
H(s) dB
FZ
Frequency
FZ 75%FLC(MASTER) FZ 0.753 1 2p LO 3 CO ---(14)
Figure 6 - Compensation network without local feedback and its asymptotic gain plot. The transfer function (Ve / VOUT) is given by: H(s) = gm3
(
R5 R6 + R5
sR4C9 ) 3 1 +sC9
---(10)
For: Lo = 6mH Co = 940mF Fz = 1.57KHz R4 = 10KV Using equations (12) and (14) to calculate C9, we get: C9 = 10000pF Choose C9 = 10000pF One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to supress the switching noise. The additional pole is given by: FP = 1 2p 3 R4 3 C9 3 CPOLE C9 + CPOLE
The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: |H(s)| = gm3 FZ = R5 3R4 R63R5 ---(12) ---(11)
1 2p3R43C9
The gain is determined by the voltage divider and E/A's transconductance gain.
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The pole sets to one half of switching frequency which results in the capacitor CPOLE: 1 1 CPOLE = p 3 R4 3 fS 1 p 3 R4 3 fS C9 fS For FP << 2 For a general solution for unconditionally stability for any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network. The typically used compensation network for voltage-mode controller is shown in Figure 7.
ZIN C10 R8 R6 Fb1 R5 VREF VOUT C12 R7 C11 Zf
As known, transconductance amplifier has high impedance (current source) output, therefore, consider should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: FP1 = 0 FP2 = FP3 = 1 2p3R83C10 1 2p3R73 FZ1 = FZ2 =
(C123C11) C12+C11
1 2p3R73C12
1 2p3R73C11 1 1 2p3C103(R6 + R8) 2p3C103R6
E/A1 Comp1
V e
Cross Over Frequency: FO1 = R73C103 VIN 1 3 VOSC 2p3Lo3Co ---(16)
Gain(dB)
H(s) dB
FZ1
FZ2
FP2
FP3
Frequency
Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Lo = Output Inductor Co = Total Output Capacitors The stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. The consideration has been taken to satisfy condition (15) regarding transconductance error amplifier. 1) Select the crossover frequency: Fo < FESR and Fo [ (1/10 ~ 1/6)3 fS 2) Select R7, so that R7 >> 2 gm
Figure 7 - Compensation network with local feedback and its asymptotic gain plot. In such configuration, the transfer function is given by: 1Ve VOUT = 1 +
gmZf gmZIN
The error amplifier gain is independent of the transconductance under the following condition:
gmZf >> 1
and
gmZIN >>1
---(15)
By replacing ZIN and Zf according to figure 7, the transformer function can be expressed as: (1+sR7C11)3[1+sC10(R6+R8)] 3 H(s)= sR6(C12+C11) 1+sR7 C12C11 3(1+sR8C10) C12+C11 1
3) Place first zero before LC's resonant frequency pole. FZ1 75% FLC C11 = 1 2p 3 FZ1 3 R7
[
(
)]
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4) Place third pole at the half of the switching frequency. FP3 = C12 = fS 2 1 2p 3 R7 3 FP3 The transfer function of power stage is expressed by: IL2(s) VIN - VOUT G(s) = = ---(17) Ve(s) sL2 3 VOSC Where: VIN = Input Voltage VOUT = Output Voltage L2 = Output Inductor VOSC = Oscillator Peak Voltage As shown the transfer function is a function of inductor current. The transfer function for the compensation network is given by equation (18), when using a series RC circuit as shown in Figure 8. D(s)= RS1 1 + sC2R2 Ve(s) = gm3 3 RS2 sC2 RS2 3 IL2(s)
IL2 L2 Fb2 Comp2 V e R2 L1 IL1 C2
C12 > 50pF If not, change R7 selection. 5) Place R7 in equation (16) and calculate C10: C10 [ 2p 3 Lo 3 FO 3 Co VOSC 3 R7 VIN
6) Place second pole at ESR zero. FP2 = FESR R8 = 1 2p 3 C10 3 FP2
(
)(
)
---(18)
1 Check if R8 > gm If R8 is too small, increase R7 and start from step 2. 7) Place second zero around the resonant frequency. FZ2 = FLC R6 = 1 - R8 2p 3 C10 3 FZ2
RS2
Vp2 RS1
E/A2
8) Use equation (1) to calculate R5: VREF R5 = 3 R6 VOUT - VREF These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load transient speed. The gain margin will be large enough to provide high DC-regulation accuracy (typically -5dB to 12dB). The phase margin should be greater than 458 for overall stability. The slave error amplifier is a differential-input transconductance amplifier as well, the main goal for the slave feed back loop is to control the inductor current to match the masters inductor current as well provides highest bandwidth and adequate phase margin for overall stability.
Figure 8 - The PI compensation network for slave channel. The loop gain function is: H(s)=[G(s)3D(s)3RS2] RS1 1+sR2C2 VIN-VOUT H(s)=RS23 gm3 RS2 3 3 sC2 sL23VOSC
(
)(
)(
)
Select a zero crossover frequency (FO2) one-tenth of the switching frequency: FO2 = fS 10
FO2 = 20KHz
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IRU3047
H(Fo)=gm3RS13R23 VIN - VOUT =1 ---(19) 2p3Fo3L23VOSC Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point.
From (19), R2 can be express as: R2 = 1 2p3FO23L23VOSC 3 gm3RS1 VIN(SLAVE) - VOUT ---(20)
Set the zero of compensator to be half of FLC(SLAVE), the compensator capacitor, C2, can be calculated as: FLC(SLAVE) = Fz = C2 = 1 2p L23COUT
FLC(SLAVE) 2 1 2p 3 R2 3 Fz ---(21)
Using equations (20) and (21) we get the following values for R2 and C2. R2 = 123K; Choose R2= 130K C2 = 1023pF; Choose C2= 1000pF
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Rev. 1.0 09/09/02
IRU3047
TYPICAL APPLICATION
Dual Input: 5V and 12V to 1.5V @ 16A 3.3V to 2.5V @ 2A
5V 12V L2 1uH C2 33uF L1 1uH C1 33uF
D1 BAT54S C3 0.1uF
C4 47uF C32 47uF
C5 330uF C31 330uF C6 1uF
VCL C8 1uF 3.3V R6 10V C13 VOUT3 47uF Q3 IRLR2703 2.5V @ 2A C30 1uF Fb3 C18 47uF R10 1K R7 1K Vcc
VcH1
VcH2 HDrv1
C9 1uF Q1 IRF7460
L3 2.2uH C14 470pF R5 4.7V
R3 5mV
C10,C11,C12 3x 150uF C15 1uF 1.5V @ 16A
LDrv1
Q2 IRF7457
U1 PGnd IRU3047 VREF
Vp2 Fb1
R8 200
R16 29.4K R21 16.5K
C24 2200pF C34 6.8nF
Comp1
Fb2 C23 1uF L4 3.3uH C26 470pF R19 4.7V R17 5mV R12 1K
C19,C20,C21 3x 150uF
Comp2
HDrv2
Q4 IRF7460
PGood C29 0.1uF
PGood SS Gnd LDrv2
Q5 IRF7457
Figure 9 - Typical application of IRU3047, configured as a 2-phase converter in current sharing mode.
Rev. 1.0 09/09/02
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13
IRU3047
TYPICAL APPLICATION
12V to 1.8V @ 8A 5V to 2.5V @ 8A 3.3V to 2.5V @ 2A
D1 12V C2 33uF L1 5V C1 33uF 1uH C3 1uF C5 1uF 3.3V C6 47uF 2.5V @ 2A Q1 IRLR2703 R1 Fb3 C7 47uF 1K R2 1K R3 C8 2200pF Comp1 22K LDrv2 R4 C9 2200uF PGood C10 0.1uF Comp2 19K PGood SS Fb2 Gnd R9 1K R5 1K Q5 IRF7457 VOUT3 C4 1uF C13 1uF C14 2x 47uF Q2 IRF7460 Q3 IRF7457 R7 442V Fb1 VREF Vp2 HDrv2 C17 2x 150uF Q4 IRF7457 L4 3.9uH 2.5V @ 8A C12 2x 150uF R8 1K L3 4.7uH LDrv1 PGnd 1.8V @ 8A C16 2x 150uF L2 1uH C11 0.1uF D2
VC L Vcc
VcH1
VcH2 HDrv1
U1 IRU3047
Figure 10 - Typical application for IRU3047 configured as two independent controllers.
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Rev. 1.0 09/09/02
IRU3047
TYPICAL APPLICATION
12V
L1 5V C1 33uF 1uH C3 1uF C5 1uF 3.3V C6 47uF 1.8V @ 2A C7 47uF Q1 IRLR2703 R1 Fb3 442 R2 1K R3 C8 16.2K 3900pF R4 C9 5600pF PGood C10 0.1uF Comp2 10K Fb2 PGood SS Vp2 Gnd R9 1K R5 VDDQ 1K Comp1 LDrv2 VOUT3 C4 1uF C13 1uF C14 150uF 1/2 Q2 IRF7313 1/2 Q2 IRF7313
VCL Vcc
VcH1
VcH2 HDrv1
1/2 D1 BAT54A LDrv1 PGnd
L2 5.6uH VDDQ= 2.5V @ 4A C16 330uF
U1 IRU3047
R7 442V C17 2x 150uF 1/2 Q3 IRF7313 1/2 Q3 IRF7313 L3 4.7uH VTT= 1.25V @ 4A C12 330uF R8 1K
Fb1 VREF HDrv2 1/2 D1 BAT54A
Figure 11 - Typical application for IRU3047 configured for DDR memory application.
Rev. 1.0 09/09/02
www.irf.com
15
IRU3047
DEMO-BOARD APPLICATION
Dual Input: 5V and 12V to 1.5V @ 12A
12V
L1, 1uH 2x 47uF, 16V Poscap C10 C21 1uF D 1 R 8 2.15 R2 2.15 Q4 IRF7811A C 2 0.1uF Q3 IRF7809A R15 4.7 V C13 470pF L3 6uH C104 1uF 1/2 D100 R12 1K 14 13 12 11 R 1 1K R13 5m V 2x 470uF Poscap
9 C20 C 33uF 16V Tn at
C 7 0.22uF
PWR OK
20 19 18 17 16 15
2.5V@12A
SS / En
VOUT 3
PGood
VcH1
HDrv1
Fb1
Gnd
Fb3
LDrv1
VCL
C18 R14 5mV
C17
C24 1uF
0V
IRU3047
Comp1 Comp2 HDrv2 VcH2 LDrv2
1 2 3 4 R103 10K C100 10000pF 5 R105 130K C101 1000pF 6 7 8 9
L4 4.7uF
C103 1uF
1/2 D100
C 4 1uF
5V
L2, 1uH C11 C12 C22 33uF 16V 2x 330uF Tn at Poscap C23 1uF Q2 IRF7811A C 3 0.1uF R 3 D 2 2.15 R 4 2.15 Q1 IRF7809A R16 4.7V C14 470pF
0V
Figure 12 - Typical application for IRU3047 configured as 2-phase converter in current sharing mode.
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PGnd
10
VREF
Vp2
Fb2
Vcc
Rev. 1.0 09/09/02
IRU3047
DEMO-BOARD APPLICATION
Application Parts List Value Qty Part# 20V, 8.5mV, 14A 2 IRF7809A 28V, 12mV, 11A 2 IRF7811A Synchronous PWM 1 IRU3047 Fast Switching 2 BAT54S Fast Switching 1 BAT54A or 1N4148 L1, L2 Inductor 1mH, 3A 2 DS1608C-102 L3 Inductor 6mH, 7.5A 1 D05022P-602HC L4 Inductor 4.7mH, 8.4A 1 D05022P-472HC C2,C3 Cap, Ceramic 0.1mF, Y5V, 25V 2 ECJ-3YB1E105K C4,21,23,24, Cap, Ceramic 1mF, Y5V, 16V 6 ECJ-2VF1C105Z 103,104 C7 Cap, Ceramic 0.22mF, Y5V, 25V 1 ECJ-3YB1E225K C101 Cap, Ceramic 1000pF, X7R, 50V 1 ECJ-2VB1H102K C9,C10 Cap, Poscap 47mF, 16V 2 16TPB47M C11,C12 Cap, Poscap 330mF, 6.3V 2 6TPB330M C13,C14 Cap, Poscap 470pF, X7R, 50V 2 ECJ-2VC1H471J C17,C18 Cap, Poscap 470mF, 6V, 40mV 2 6TPB470M C20,C22 Cap, Tantulum 33mF, 16V 2 EC-T1CD336R C100 Cap, Ceramic 10000pF 1 R1,R12 Resistor 1K, 1% 2 R2,3,4,8 Resistor 2.15V 4 R13,R14 Resistor 5mV, 1W, 1% 2 ERJ-M1WSF5MOU R15,R16 Resistor 4.7V 2 R103 Resistor 10K 1 R105 Resistor 130K 1 Ref Desig Q1, Q3 Q2, Q4 U1 D1, D2 D100 * Description MOSFET MOSFET Controller Diode Diode Manuf Web site (www.) IR irf.com IR IR IR IR Any Coilcraft coilcraft.com Coilcraft Coilcraft Panasonic maco.panasonic.co.jp Panasonic Panasonic Panasonic Sanyo Sanyo Panasonic Sanyo Panasonic
sanyo.com/industrial maco.panasonic.co.jp sanyo.com/industrial maco.panasonic.co.jp
* Use this diode for (source/sink, no load) applications when the inductor current goes negative and for the fast load transient from full output load to no load.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01
Rev. 1.0 09/09/02
www.irf.com
17
IRU3047
(W) SOIC Package 20-Pin Surface Mount, Wide Body
H
A B C
R
E
DETAIL-A PIN NO. 1
D
0.5160.020 x 458
L
DETAIL-A K F T I
G
J
SYMBOL A B C D E F G I J K L R T
20-PIN MIN MAX 12.598 12.979 1.018 1.524 0.66 REF 0.33 0.508 7.40 7.60 2.032 2.64 0.10 0.30 0.229 0.32 10.008 10.654 08 88 0.406 1.270 0.63 0.89 2.337 2.642
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
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Rev. 1.0 09/09/02
IRU3047
PACKAGE SHIPMENT METHOD
PKG DESIG W PACKAGE DESCRIPTION SOIC, Wide Body PIN COUNT 20 PARTS PER TUBE 38 PARTS PER REEL 1000 T&R Orientation Fig A
1
1
1
Feed Direction Figure A
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01
Rev. 1.0 09/09/02
www.irf.com
19

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